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EL5221
Data Sheet July 25, 2007 FN7187.2
Dual 12MHz Rail-to-Rail Input-Output Buffer
The EL5221 is a dual, low power, high voltage rail-to-rail input-output buffer. Operating on supplies ranging from 5V to 15V, while consuming only 500A per channel, the EL5221 has a bandwidth of 12MHz -(-3dB). The EL5221 also provides rail-to-rail input and output ability, giving the maximum dynamic range at any supply voltage. The EL5221 also features fast slewing and settling times, as well as a high output drive capability of 30mA (sink and source). These features make the EL5221 ideal for use as voltage reference buffers in Thin Film Transistor Liquid Crystal Displays (TFT-LCD). Other applications include battery power, portable devices, and anywhere low power consumption is important. The EL5221 is available in space-saving 6 Ld SOT-23 and 8 Ld MSOP packages and operates over a temperature range of -40C to +85C.
Features
* 12MHz -3dB bandwidth * Unity gain buffer * Supply voltage = 4.5V to 16.5V * Low supply current (per buffer) = 500A * High slew rate = 10V/s * Rail-to-rail operation * Pb-Free plus anneal available (RoHS compliant)
Applications
* TFT-LCD drive circuits * Electronics notebooks * Electronics games * Personal communication devices * Personal Digital Assistants (PDA) * Portable instrumentation
Ordering Information
PART NUMBER EL5221CW-T7* EL5221CW-T7A* EL5221CWZ-T7* (Note) PART MARKING M M BBEA PACKAGE 6 Ld SOT-23 6 Ld SOT-23 6 Ld SOT-23 (Pb-free) 6 Ld SOT-23 (Pb-free) 8 Ld MSOP 8 Ld MSOP 8 Ld MSOP 8 Ld MSOP (Pb-free) 8 Ld MSOP (Pb-free) 8 Ld MSOP (Pb-free) PKG. DWG. # MDP0038 MDP0038 MDP0038 MDP0038 MDP0043 MDP0043 MDP0043 MDP0043
* Wireless LANs * Office automation * Active filters * ADC/DAC buffer
Pinouts
EL5221 (6 LD SOT-23) TOP VIEW
VINA 1 VS- 2 VINB 3 6 VOUTA 5 VS+ 4 VOUTB
EL5221CWZ-T7A* BBEA (Note) EL5221CY EL5221CY-T7* EL5221CY-T13* EL5221CYZ (Note) EL5221CYZ-T7* (Note) EL5221CYZ-T13* (Note) K K K BAAAJ BAAAJ BAAAJ
MDP0043 MDP0043 EL5221 (8 LD MSOP) TOP VIEW
VOUTA 1 NC 2 VINA 3 VS- 4 8 VS+ 7 VOUTB 6 NC 5 VINB
*Please refer to TB347 for details on reel specifications. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2002, 2005, 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
EL5221
Absolute Maximum Ratings (TA = +25C)
Supply Voltage between VS+ and VS- . . . . . . . . . . . . . . . . . . . .+18V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . VS- - 0.5V, VS+ +0.5V Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 30mA ESD Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2kV
Thermal Information
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Operating Temperature . . . . . . . . . . . . . . . . . . . . . . .-40C to +85C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
Electrical Specifications
PARAMETER
VS+ = +5V, VS- = -5V, RL = 10k and CL = 10pF to 0V, TA = +25C unless otherwise specified. CONDITION MIN (Note 3) TYP MAX (Note 3) UNIT
DESCRIPTION
INPUT CHARACTERISTICS VOS TCVOS IB RIN CIN AV Input Offset Voltage Average Offset Voltage Drift Input Bias Current Input Impedance Input Capacitance Voltage Gain -4.5V VOUT 4.5V 0.995 VCM = 0V (Note 1) VCM = 0V 2 5 2 1 1.35 1.005 50 12 mV V/C nA G pF V/V
OUTPUT CHARACTERISTICS VOL VOH ISC Output Swing Low Output Swing High Short Circuit Current IL = -5mA IL = 5mA Short to GND 4.85 -4.92 4.92 120 -4.85 V V mA
POWER SUPPLY PERFORMANCE PSRR IS Power Supply Rejection Ratio Supply Current (Per Buffer) VS is moved from 2.25V to 7.75V No load 60 80 500 750 dB A
DYNAMIC PERFORMANCE SR tS BW CS Slew Rate (Note 2) Settling to +0.1% -3dB Bandwidth Channel Separation -4.0V VOUT 4.0V, 20% to 80% VO = 2V step RL = 10k, CL = 10pF f = 5MHz 7 10 500 12 75 V/s ns MHz dB
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FN7187.2 July 25, 2007
EL5221
Electrical Specifications
PARAMETER VS+ = +5V, VS- = 0V, RL = 10k and CL = 10pF to 2.5V, TA = +25C unless otherwise specified. CONDITION MIN (NOTE 3) TYP MAX (NOTE 3) UNIT
DESCRIPTION
INPUT CHARACTERISTICS VOS TCVOS IB RIN CIN AV Input Offset Voltage Average Offset Voltage Drift Input Bias Current Input Impedance Input Capacitance Voltage Gain 0.5 VOUT 4.5V 0.995 VCM = 2.5V (Note 1) VCM = 2.5V 2 5 2 1 1.35 1.005 50 10 mV V/C nA G pF V/V
OUTPUT CHARACTERISTICS VOL VOH ISC Output Swing Low Output Swing High Short Circuit Current IL = -5mA IL = 5mA Short to GND 4.85 80 4.92 120 150 mV V mA
POWER SUPPLY PERFORMANCE PSRR IS Power Supply Rejection Ratio Supply Current (Per Buffer) VS is moved from 4.5V to 15.5V No Load 60 80 500 750 dB A
DYNAMIC PERFORMANCE SR tS BW CS Slew Rate (Note 2) Settling to +0.1% -3dB Bandwidth Channel Separation 1V VOUT 4V, 20% to 80% VO = 2V Step RL = 10k, CL = 10pF f = 5MHz 7 10 500 12 75 V/s ns MHz dB
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FN7187.2 July 25, 2007
EL5221
Electrical Specifications
PARAMETER VS+ = +15V, VS- = 0V, RL = 10k and CL = 10pF to 7.5V, TA = +25C unless otherwise specified. CONDITION MIN (NOTE 3) TYP MAX (NOTE 3) UNIT
DESCRIPTION
INPUT CHARACTERISTICS VOS TCVOS IB RIN CIN AV Input Offset Voltage Average Offset Voltage Drift Input Bias Current Input Impedance Input Capacitance Voltage Gain 0.5 VOUT 14.5V 0.995 VCM = 7.5V (Note 1) VCM = 7.5V 2 5 2 1 1.35 1.005 50 14 mV V/C nA G pF V/V
OUTPUT CHARACTERISTICS VOL VOH ISC Output Swing Low Output Swing High Short Circuit Current IL = -5mA IL = 5mA Short to GND 14.85 80 14.92 120 150 mV V mA
POWER SUPPLY PERFORMANCE PSRR IS Power Supply Rejection Ratio Supply Current (Per Buffer) VS is moved from 4.5V to 15.5V No Load 60 80 500 750 dB A
DYNAMIC PERFORMANCE SR tS BW CS NOTES: 1. Measured over the operating temperature range. 2. Slew rate is measured on rising and falling edges. 3. Parts are 100% tested at +25C. Over-temperature limits established by characterization and are not production tested. Slew Rate (Note 2) Settling to +0.1% -3dB Bandwidth Channel Separation 1V VOUT 14V, 20% to 80% VO = 2V Step RL = 10k, CL = 10pF f = 5MHz 7 10 500 12 75 V/s ns MHz dB
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FN7187.2 July 25, 2007
EL5221 Typical Performance Curves
Input Offset Voltage Distribution 2000 1600 Quantity (Buffers) 1200 800 400 0 0 2 4 6 -8 -6 -4 -12 -10 -2 8 10 12 Input Offset Voltage (mV) VS=5V TA=25C Typical Production Distribution Quantity (Buffers) 35 30 25 20 15 10 5 0 1 3 5 7 9 11 13 15 17 Input Offset Voltage, TCVOS (V/C) 19 150 150 VS=5V TA=25C Typical Production Distribution Input Offset Voltage Drift
Input Offset Voltage vs Temperature 10 4
Input Bias Current vs Temperature
Input Offset Voltage (mV)
VS=5V
Input Bias Current (nA)
5
2
VS=5V
0
0
-5
-2
-10 -50
0
50 Temperature (C)
100
150
-4 -50
0
50 Temperature (C)
100
Output High Voltage vs Temperature 4.97 VS=5V IOUT=5mA Output High Voltage (V) 4.96 Output Low Voltage (V) -4.91 -4.92 -4.93 -4.94 -4.95 -4.96 4.93 -50
Output Low Voltage vs Temperature
VS=5V IOUT=-5mA
4.95
4.94
0
50 Temperature (C)
100
150
-4.97 -50
0
50 Temperature (C)
100
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FN7187.2 July 25, 2007
EL5221 Typical Performance Curves
(Continued)
Voltage Gain vs Temperature 1.001 13 12.5 1.0005 Voltage Gain (V/V) Slew Rate (V/S) VS=5V 12 11.5 11 10.5 0.999 -50
Slew Rate vs Temperature
VS=5V
1.0000
0.9995
0
50 Temperature (C)
100
150
10 -50
0
50 Temperature (C)
100
150
Supply Current per Channel vs Temperature 0.55 650
Supply Current per Channel vs Supply Voltage
VS=5V Supply Current (mA) 0.5 Supply Current (A)
550
TA=25C
450
0.45
350
0.4 -50
0
50 Temperature (C)
100
150
250 0 5 10 Supply Voltage (V) 15 20
Frequency Response for Various RL 5 Magnitude (Normalized) (dB) Magnitude (Normalized) (dB) 10k 0 CL=10pF VS=5V 1k 560 150 20 10 0
Frequency Response for Various CL
RL=10k VS=5V 12pF 50pF
-5
-10 -20 1000pF -30 100k
100pF
-10
-15 100k
1M
10M
100M
Frequency (Hz)
1M 10M Frequency (Hz)
100M
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FN7187.2 July 25, 2007
EL5221 Typical Performance Curves
(Continued)
Output Impedance vs Frequency 200 160 120 80 40 0 10k VS=5V TA=25C Maximum Output Swing (VP-P) 12 10 8 6 4 2
Maximum Output Swing vs Frequency
Output Impedance ()
VS=5V TA=25C RL=10k CL=12pF Distortion <1%
100k 1M Frequency (Hz)
10M
0 10k
100k 1M Frequency (Hz)
10M
PSRR vs Frequency 80 PSRR+ Voltage Noise (nV/Hz) PSRR600
Input Voltage Noise Spectral Density vs Frequency
60 PSRR (dB)
100
40
10
20
VS=5V TA=25C
0 100
1k
10k 100k Frequency (Hz)
1M
10M
1 100
1k
10k 100k 1M Frequency (Hz)
10M
100M
Total Harmonic Distortion + Noise vs Frequency 0.010 0.009 0.008 THD+ N (%) X-Talk (dB) 0.007 0.006 0.005 0.004 0.003 0.002 0.001 1k 10k Frequency (Hz) 100k VS=5V RL=10k VIN=1VRMS -80 -60
Channel Separation vs Frequency Response Dual measured Channel A to B Quad measured Channel A to D or B to C Other combinations yield improved rejection. VS=5V RL=10k VIN=220mVRMS
-100
-120
-140 1k
10k
100k Frequency (Hz)
1M
6M
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FN7187.2 July 25, 2007
EL5221 Typical Performance Curves
(Continued)
Small-Signal Overshoot vs Load Capacitance 100 80 Overshoot (%) 60 40 20 0 10 VS=5V RL=10k VIN=50mV TA=25C 5 4 3 2 Step Size (V) 1 0 -1 -2 -3 -4 -5 100 Load Capacitance (pF) 1000
Settling Time vs Step Size
VS=5V RL=10k CL=12pF TA=25C
0.1%
0.1%
0
200
400 Settling Time (nS)
600
800
Large Signal Transient Response
Small Signal Transient Response 50mV 200ns
1V
1S
VS=5V TA=25C RL=10k CL=12pF
VS=5V TA=25C RL=10k CL=12pF
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FN7187.2 July 25, 2007
EL5221 Pin Descriptions
6 LD SOT-23 8 LD MSOP PIN NAME 1 3 VINA FUNCTION Buffer A Input EQUIVALENT CIRCUIT
VS+
VSCircuit 1
2 3 4
4 5 7
VSVINB VOUTB
Negative Supply Voltage Buffer B Input Buffer B Output (Reference Circuit 1)
VS+
VSGND Circuit 2
5 6
8 1
VS+ VOUTA
Positive Supply Voltage Buffer A Output
.
(Reference Circuit 2)
Applications Information
Product Description
The EL5221 unity gain buffer is fabricated using a high voltage CMOS process. It exhibits rail-to-rail input and output capability and has low power consumption (500A per buffer). These features make the EL5221 ideal for a wide range of general-purpose applications. When driving a load of 10k and 12pF, the EL5221 has a -3dB bandwidth of 12MHz and exhibits 10V/s slew rate.
5V
10S
VS=5V TA=25C VIN=10VP-P
5V
Operating Voltage, Input, and Output
The EL5221 is specified with a single nominal supply voltage from 5V to 15V or a split supply with its total range from 5V to 15V. Correct operation is guaranteed for a supply range of 4.5V to 16.5V. Most EL5221 specifications are stable over both the full supply range and operating temperatures of -40C to +85C. Parameter variations with operating voltage and/or temperature are shown in the typical performance curves. The output swings of the EL5221 typically extend to within 80mV of positive and negative supply rails with load currents of 5mA. Decreasing load currents will extend the output voltage range even closer to the supply rails. Figure 1 shows the input and output waveforms for the device. Operation is from 5V supply with a 10k load connected to GND. The input is a 10VP-P sinusoid. The output voltage is approximately 9.985VP-P.
FIGURE 1. OPERATION WITH RAIL-TO-RAIL INPUT AND OUTPUT
Short Circuit Current Limit
The EL5221 will limit the short circuit current to 120mA if the output is directly shorted to the positive or the negative supply. If an output is shorted indefinitely, the power dissipation could easily increase such that the device may be damaged. Maximum reliability is maintained if the output continuous current never exceeds 30mA. This limit is set by the design of the internal metal interconnects.
Output Phase Reversal
The EL5221 is immune to phase reversal as long as the input voltage is limited from VS- -0.5V to VS+ +0.5V. Figure 2 shows a photo of the output of the device with the input voltage driven beyond the supply rails. Although the device's output will not change phase, the input's overvoltage should be avoided. If an input voltage exceeds supply voltage by
FN7187.2 July 25, 2007
9
Output
Input
EL5221
more than 0.6V, electrostatic protection diodes placed in the input stage of the device begin to conduct and overvoltage damage could occur.
1V 10S
where: i = 1 to 2 for dual buffer VS = Total supply voltage ISMAX = Maximum supply current per channel VOUTi = Maximum output voltage of the application ILOADi = Load current
VS=2.5V TA=25C VIN=6VP-P
1V
FIGURE 2. OPERATION WITH BEYOND-THE-RAILS INPUT
Power Dissipation
With the high-output drive capability of the EL5221 buffer, it is possible to exceed the +125C "absolute-maximum junction temperature" under certain load current conditions. Therefore, it is important to calculate the maximum junction temperature for the application to determine if load conditions need to be modified for the buffer to remain in the safe operating area. The maximum power dissipation allowed in a package is determined according to:
T JMAX - T AMAX P DMAX = ------------------------------------------- JA (EQ. 1)
If we set the two PDMAX equations equal to each other, we can solve for RLOADi to avoid device overheat. Figure 3 and Figure 4 provide a convenient way to see if the device will overheat. The maximum safe power dissipation can be found graphically, based on the package type and the ambient temperature. By using the previous equation, it is a simple matter to see if PDMAX exceeds the device's power derating curves. To ensure proper operation, it is important to observe the recommended derating curves shown in Figure 3 and Figure 4.
Package Mounted on a JEDEC JESD51-7 High Effective Thermal Conductivity Test Board 1 870mW 0.8 Power Dissipation (W)
M
MAX TJ=125C
0.6 435mW 0.4 0.2 0 0 25
SO
P8
11
5 C /W
SO T2 3-6
23 0C /W
where: TJMAX = Maximum junction temperature TAMAX = Maximum ambient temperature JA = Thermal resistance of the Package PDMAX = Maximum power dissipation in the package The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the loads, or:
Power Dissipation (W)
50 75 85 100 Ambient Temperature (C)
125
150
FIGURE 3. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
0.6 0.5 0.4 0.3 0.2 0.1
Package Mounted on a JEDEC JESD51-3 Low Effective Thermal Conductivity Test Board 486mW 391mW
M SO P8
MAX TJ=125C
P DMAX = i [ V S x I SMAX + ( V S + - V OUT i ) x I LOAD i ]
(EQ. 2)
SO T2 36
20
6 C/ W
when sourcing, and:
P DMAX = i [ V S x I SMAX + ( V OUT i - V S - ) x I LOAD i ] (EQ. 3)
25 6 C/ W
0 0 25 50 75 85 100 125 150 Ambient Temperature (C)
when sinking.
FIGURE 4. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
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FN7187.2 July 25, 2007
EL5221
Unused Buffers
It is recommended that any unused buffer have the input tied to the ground plane.
Driving Capacitive Loads
The EL5221 can drive a wide range of capacitive loads. As load capacitance increases, however, the -3dB bandwidth of the device will decrease and the peaking increase. The buffers drive 10pF loads in parallel with 10k with just 1.5dB of peaking, and 100pF with 6.4dB of peaking. If less peaking is desired in these applications, a small series resistor (usually between 5 and 50) can be placed in series with the output. However, this will obviously reduce the gain slightly. Another method of reducing peaking is to add a "snubber" circuit at the output. A snubber is a shunt load consisting of a resistor in series with a capacitor. Values of 150 and 10nF are typical. The advantage of a snubber is that it does not draw any DC load current or reduce the gain
Power Supply Bypassing and Printed Circuit Board Layout
The EL5221 can provide gain at high frequency. As with any high frequency device, good printed circuit board layout is necessary for optimum performance. Ground plane construction is highly recommended, lead lengths should be as short as possible, and the power supply pins must be well bypassed to reduce the risk of oscillation. For normal single supply operation, where the VS- pin is connected to ground, a 0.1F ceramic capacitor should be placed from VS+ to pin to VS- pin. A 4.7F tantalum capacitor should then be connected in parallel, placed in the region of the buffer. One 4.7F capacitor may be used for multiple devices. This same capacitor combination should be placed at each supply pin to ground if split supplies are to be used.
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FN7187.2 July 25, 2007
EL5221 SOT-23 Package Family
e1 A N 6 4
MDP0038
D
SOT-23 PACKAGE FAMILY MILLIMETERS SYMBOL A A1 SOT23-5 1.45 0.10 1.14 0.40 0.14 2.90 2.80 1.60 0.95 1.90 0.45 0.60 5 SOT23-6 1.45 0.10 1.14 0.40 0.14 2.90 2.80 1.60 0.95 1.90 0.45 0.60 6 TOLERANCE MAX 0.05 0.15 0.05 0.06 Basic Basic Basic Basic Basic 0.10 Reference Reference Rev. F 2/07 NOTES:
E1 2 3
E
A2 b c
0.20 C
0.15 C D 2X 5 e B b NX 1 2 3 2X 0.20 M C A-B D
D E E1 e e1 L L1 N
0.15 C A-B 2X C D
1
3
A2 SEATING PLANE 0.10 C NX A1
1. Plastic or metal protrusions of 0.25mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25mm maximum per side are not included. 3. This dimension is measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 5. Index area - Pin #1 I.D. will be located within the indicated zone (SOT23-6 only).
(L1)
H
6. SOT23-5 version has no center lead (shown as a dashed line).
A
GAUGE PLANE c L 0 +3 -0
0.25
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FN7187.2 July 25, 2007
EL5221 Mini SO Package Family (MSOP)
0.25 M C A B D N A (N/2)+1
MDP0043
MINI SO PACKAGE FAMILY MILLIMETERS SYMBOL A A1 MSOP8 1.10 0.10 0.86 0.33 0.18 3.00 4.90 3.00 0.65 0.55 0.95 8 MSOP10 1.10 0.10 0.86 0.23 0.18 3.00 4.90 3.00 0.50 0.55 0.95 10 TOLERANCE Max. 0.05 0.09 +0.07/-0.08 0.05 0.10 0.15 0.10 Basic 0.15 Basic Reference NOTES 1, 3 2, 3 Rev. D 2/07 NOTES: 1. Plastic or metal protrusions of 0.15mm maximum per side are not included.
E
E1
PIN #1 I.D.
A2 b c
B
1 (N/2)
D E E1
e C SEATING PLANE 0.10 C N LEADS b
H
e L L1 N
0.08 M C A B
L1 A c SEE DETAIL "X"
2. Plastic interlead protrusions of 0.25mm maximum per side are not included. 3. Dimensions "D" and "E1" are measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994.
A2 GAUGE PLANE L DETAIL X
0.25
A1
3 3
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 13
FN7187.2 July 25, 2007

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